`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:22:28 09/16/2012 
// Design Name: 
// Module Name:    sram 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module sram(write_enable_i,enable_i,data_o,address_i,clk_i,data_i
    );
	 
	 input write_enable_i,enable_i,clk_i;
	 input [3:0] address_i,data_i;
	 output [3:0] data_o;

	parameter RAM_WIDTH = 16;
   parameter RAM_ADDR_BITS = 8;

   reg [RAM_WIDTH-1:0] sram [(2**RAM_ADDR_BITS)-1:0];
   reg [RAM_WIDTH-1:0] data_o;

  always @(posedge clk_i) begin
      if (!enable_i) begin
         if (!write_enable_i) begin
            sram[address_i] <= data_i;
			end
			else if (write_enable_i) begin
         data_o <= sram[address_i];
			end
		end
	end

endmodule
